1. Field of the Invention
The method and apparatus of the present invention generally relates to a method for recovering from a memory read error in an instruction word used to control a programmable device and, more particularly, to a method for recovering from a control store memory read error of a microinstruction in a microprogrammed electronic data processing system.
2. Background of the Invention
It is common practice today to implement data processing systems in which the software instruction is executed by use of microprocessors which are firmware controlled. In this system, the firmware is stored as a series of microinstructions in a memory referred to as a control store. The control store may be a random access memory (RAM) which can be written into, as well as read from, or it may be a read only memory (ROM) of one type or another. In either case, as the use of firmware increases with more of the logic of systems being microprogrammable, and as faster memories are used in order to decrease the time required to perform operations, it is becoming more likely that a read error will occur when microinstructions are read from the control store. Many of the errors which occur when reading data from RAMs and ROMs are of a transient nature and will not recur if the same data is read a second time from the memory.
One method of detecting a memory read error is to store one or more parity bits with the instructions and to compute the parity of the instruction read from memory and compare it with the parity bit or bits stored with the instruction and if there is a mismatch to go back and read the instruction again. Although this scheme works, it has the disadvantage that execution of the program is delayed because an instruction cannot be executed until its parity is computed and compared with the stored parity.
One method of overcoming this delay associated with checking the parity of each instruction before it is executed is to prefetch instructions so that the parity of one instruction can be checked while a previously checked instruction is being executed. Although this scheme can be used to advantage to eliminate the delays associated with checking parity prior to instruction execution, it has the disadvantage that it can become quite complex and therefore costly because the execution of one instruction will often determine which is the next instruction to be executed and therefore prefetching the "next" instruction can be very complicated or impossible. One method of simplifying this prefetch problem is to prefetch the "normal next" instruction and check it for possible read errors and if the normal next instruction turns out not to be the "next" instruction, the "normal next" instruction is discarded (i.e., flushed from a buffer) and the system waits while the "next" instruction is read and checked. Even this "flushing" scheme can be complex and still result in delays each time the instructions aren't executed in the "normal" sequence.
Therefore, what is needed is a method of detecting and correcting instruction memory read errors which is simple and which does not adversely effect the execution time of the system.